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W631GG6KB
8.19.2.3 ODT during Reads
As the DDR3 SDRAM can not terminate and drive at the same time, R TT must be disabled at least half a clock cycle before the read preamble by driving
the ODT pin low appropriately. R TT may not be enabled until the end of the post-amble as shown in the example below. As shown in Figure 76 below, at
cycle T15, DRAM turns on the termination when it stops driving, which is determined by t HZ . If DRAM stops driving early (i.e., t HZ is early), then t AON min
timing may apply. If DRAM stops driving late (i.e., t HZ is late), then DRAM complies with t AON max timing. Note that ODT may be disabled earlier before the
Read and enabled later after the Read than shown in this example in Figure 76.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
VALID
ODTLon = CWL + AL - 2
ODTTLoff = CWL + AL - 2
ODT
t AOFmin
RTT
Rtt_Nom
t AOFmax
t AONmax
Rtt_Nom
RL = AL + CL
DQS, DQS#
DQ
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
TRANSITIONING
DON'T CARE
Figure 76 – ODT must be disabled externally during Reads by driving ODT low.
(CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8)
Publication Release Date: Dec. 09, 2013
Revision A05
- 82 -
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